A. Prior Art
FIG. 16 shows a conventional circuit for controlling the energization of the printing wires A and B of a serial dot-matrix printer in which two printing wires A and B are arranged at a distance every three dots in the printing direction (at a dot pitch of 4 for the printing wires) and moved in the printing direction while a printing medium is fixed. A data distribution circuit 200 receives a series of data including printing data (binary "1") indicating characters or images are to be printed at predetermined dot positions and non-printing data (binary "0") indicating that the characters or images are not to be printed and distributes alternately the printing data ("1") to the two wires A and B.
The data distribution circuit 200 comprises a synchronous flip-flop (hereinafter called "D-FF") 221, an exclusive OR gate (hereinafter abbreviated "XOR gate") 222, an inverter 223, AND gates 224 and 225, and a shift register 226. The shift register; 226 comprises four D-FFs 226P, 226Q, 226R, and 226S connected in series which correspond to the distance of three dots, that is, at a dot pitch of 4 between the wires A and B. A Q output of D-FF 221 is connected to one input of the XOR gate 222 and printing data and non-printing data are provided to the other input of the XOR gate 222. An output of the XOR gate 222 is connected not only to an input of the inverter 223 and one input of the AND gate 224, but to a D input of the D-FF 221. An output of the inverter 223 is connected to one input of the AND gate 225. To the other input of the AND gate 224 and the other input of the AND gate 225, printing data ("1") and non-printing data ("0") are provided. An output of the AND gate 225 is connected to an input of the first D-FF 226P of the shift register 226. Clock inputs of the D-FF 221 and the D-FFs 226P, 226Q, 226R, and 226S of the shift register are supplied with a continuous series of dot clock pulses indicating dot positions.
FIG. 17 shows the time charts of the operation of each part of the circuit shown in FIG. 16. As shown in FIG. 17, the output of the XOR gate 222 holds "1" (printing data) while receiving printing data ("1") and then subsequent printing data ("1"), even if non-printing data ("0") is received in a state where the subsequent printing data ("1") is not reached and then becomes "0" at a time when the subsequent printing data ("1") is reached. Printing data ("1") are alternately provided, through the AND gates 224 and 225, to the wires A and then B, respectively. The supply of printing data to the wire B is delayed by the four dot-time shift register 226 to compensate by three dots corresponding to a distance between the wires A and B. Printing data are distributed alternately to the wires A and B to accomplish high-speed printing, because a time is required for printing by a wire (for example, wire A) then following printing and therefore to accomplish high-speed printing, it is necessary to do printing by one wire (for example, wire B) while the other wire (for example, wire A) waits for printing.
FIG. 18 shows the assignment of printing data to the wires A and B in a case where continuous dots are printed by the wires A and B at a distance corresponding to three dots, that is, at a dot pitch of 4, as shown in FIG. 16.
FIG. 19 shows timing for driving the wires A and B and the energization of the wires A and B in a case where printing data are distributed, as shown in FIG. 18, to the wires A and B.
A circuit similar to the circuit shown in FIG. 16 is disclosed by Japanese Patent Application No. 1-309397.
B. Problem to be Solved by the Invention
FIG. 20 shows a sequence of eight dot lines each of which indicates five continuous dot positions P1, P2, P3, P4, and P5 in the printing direction and is assigned printing data at the first position P1 and the last positions P5. In the figure, circles and marks X indicate printing data and non-printing data, respectively. A or B in a circle indicates that printing data is distributed to the wire A or B, respectively. The conventional circuit shown in FIG. 16 assigns printing data alternately to the wires A and B and printing data are thus assigned as shown in FIG. 20.
In cases of (1), (5), (6), and (7) of FIG. 20, that is, cases where two printing data exist at a distance (of three dots) between the two printing wires A and B and no printing data exists or even printing data are present between the two printing data, the wires A and B are simultaneously energized to cause driving current to concentrate, that is, to increase driving current by twice that of printing by only one wire.
Japanese PUPA 57-160658 discloses that a distance between one printing element array comprising twelve printing wires and the other printing element array comprising 12 printing wires is set to several dots plus and a half dot to avoid a simultaneous energization of the two printing element arrays for one printing and to reduce peak current to be consumed to half. Such prior art, however, causes generation of timing signals to be complicated, since the distance between the two printing element arrays is not set to integral dots.
Japanese PUPA 61-74854 discloses that a distance between one printing element array and the other printing element array is set to n 1/2 m times of a basic pitch of a printing dot (n=1, 2, ..; m=2, 3, ..) to avoid a simultaneous energization of the two printing element arrays for one printing when high-density printing such as double-density or triple-density printing is done and to reduce consuming peak current. The prior art, however, causes generation of timing signals to be complicated since the distance between two printing element arrays is not set to integral dots.